Title :
Comparison of high-performance VLSI adders in the energy-delay space
Author :
Oklobdzija, Vojin G. ; Zeydel, Bart R. ; Dao, Hoang Q. ; Mathew, Sanu ; Krishnamurthy, Ram
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of California, Davis, CA, USA
fDate :
6/1/2005 12:00:00 AM
Abstract :
In this paper, we motivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, not requiring extensive simulation or use of computer-aided design tools, yet sufficiently accurate to provide guidance through various choices in the design process. We demonstrate the accuracy of the method by applying it to examples of high-performance 32- and 64-b adders in 100- and 130-nm CMOS technologies.
Keywords :
CMOS logic circuits; VLSI; adders; digital arithmetic; logic design; 100 nm; 130 nm; 32 bit; 64 bit; CMOS technology; VLSI adders; design process; digital arithmetic; digital circuits; energy-delay characteristics; energy-delay optimization; estimation technique; Adders; CMOS technology; Computational modeling; Delay estimation; Digital arithmetic; Laboratories; Process design; Space technology; Topology; Very large scale integration; Adders; digital arithmetic; digital circuits; energy-delay optimization;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2005.848819
