Title :
6-bit 25 MHz NMOS parallel A/D convertor
Author :
Fielder, H.L. ; Zimmer, G.
Author_Institution :
Universitÿt Dortmund, Lehrstuhl Bauelemente der Elektrotechnik, Dortmund, West Germany
Abstract :
A standard silicon gate NMOS enhancement/deplection process with 4 ¿m minimum channel length has been applied in the design of a 6-bit parallel A/D converter. The chip features a conversion rate of 25 MHz (MSPS), 8.5 MHz analogue input signal bandwidth and small chip size of 4.9 mm2.
Keywords :
analogue-digital conversion; field effect integrated circuits; 6-bit parallel A/D convertor; ADC; Si-gate NMOS; channel length; conversion rate 25 MHz; enhancement/depletion process; input signal bandwidth 8.5 MHz;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830241
