Device performance of transistors with high-κ dielectrics using cross-wafer-scaled interface-layer thickness

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO₂ interface layer between a silicon substrate and high-κ dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO₂ interface. This technique provides a powerful tool in examining the effect of the process variations on device performance.