An ultra-shallow buried-channel PMOST using boron penetration

A novel process using controlled boron penetration to form an ultrashallow buried-layer for a sub-half-micrometer channel-length n⁺ polysilicon-gate PMOS device is presented. Experimental results coupled with two-dimensional process and device simulation are used to examine the impact of the buried-channel design on the drain-induced barrier lowering effects. Using a sacrificial 125-Å gate oxide and a BF₂-implanted polysilicon layer, the boron penetration profile is formed prior to the actual gate oxidation. This process is suitable for sub-half-micrometer channel-length n⁺ poly-gated CMOS technologies which require gate oxide thicknesses of less than 100 Å