• DocumentCode
    985821
  • Title

    Scaling theory for double-gate SOI MOSFET´s

  • Author

    Suzuki, Kunihiro ; Tanaka, Tetsu ; Tosaka, Yoshiharu ; Horie, Hiroshi ; Arimoto, Yoshihiro

  • Author_Institution
    Fujitsu Labs. Ltd., Atsugi, Japan
  • Volume
    40
  • Issue
    12
  • fYear
    1993
  • fDate
    12/1/1993 12:00:00 AM
  • Firstpage
    2326
  • Lastpage
    2329
  • Abstract
    A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness tsi; gate oxide thickness tox) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 μm while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator
  • Keywords
    insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; 0.1 mum; S-factor; Si-SiO2; device design; double-gate SOI MOSFET; gate length; gate oxide thickness; numerical simulation; scaling theory; silicon thickness; subthreshold factor; two-dimensional device simulator; Capacitance; Degradation; Dielectric constant; Doping; Guidelines; MOSFET circuits; Poisson equations; Silicon compounds; Transconductance; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.249482
  • Filename
    249482
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=985821