Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

Author

Henzler, Stephan ; Georgakos, Georg ; Eireiner, Matthias ; Nirschl, Thomas ; Pacha, Christian ; Berthold, Joerg ; Schmitt-Landsiedel, Doris

Author_Institution

Infineon Technol. AG, Munich-Neubiberg

Volume

41

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

1654

Lastpage

1661

Abstract

Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps

Keywords

flip-flops; logic design; logic gates; circuit logical state; fine-grained power gating; flip-flops; idle circuit blocks; sleep transistor scheme; stand-by power consumption; state retention; Energy consumption; Flip-flops; Leakage current; Logic circuits; Power supplies; Propagation delay; Rails; Subthreshold current; System-on-a-chip; Tunneling; Leakage reduction; MTCMOS; low power; power gating; retention flip-flop; sleep transistor; state retention;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.873218

Filename

1644877