• DocumentCode
    986056
  • Title

    Run-length-limited low-density Parity check codes based on deliberate error insertion

  • Author

    Vasic, Bane ; Pedagani, Karunakar

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA
  • Volume
    40
  • Issue
    3
  • fYear
    2004
  • fDate
    5/1/2004 12:00:00 AM
  • Firstpage
    1738
  • Lastpage
    1743
  • Abstract
    We propose a novel approach to modulation and error control coding. The idea is to completely eliminate a constrained encoder and, instead, impose the constraint by the deliberate introduction of bit errors before transmission. The redundancy that would have been used for imposing the constraint is used in our scheme to strengthen the error control code (ECC), in such a way that the ECC becomes capable of correcting both deliberate errors as well as channel errors that occur during the detection. Our ECC-modulation scheme is based on iterative decoding of low-density parity check codes and a run-length constraint.
  • Keywords
    error correction codes; iterative decoding; modulation coding; parity check codes; runlength codes; ECC-modulation scheme; bit errors insertion; channel errors; constrained encoder; deliberate error insertion; error control coding; iterative decoding; low-density parity check codes; modulation coding; run-length constraint; run-length-limited constraint; run-length-limited parity check codes; Algorithm design and analysis; Automata; Block codes; Decoding; Error correction; Error correction codes; Interference constraints; Modulation coding; Parity check codes; Redundancy; Combined constrained and error control coding; low-density parity check codes; modulation coding; run-length-limited constraint;
  • fLanguage
    English
  • Journal_Title
    Magnetics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9464
  • Type

    jour

  • DOI
    10.1109/TMAG.2004.826904
  • Filename
    1298953