Title :
Minimisation of on-resistance of VDMOS power FETs
Author :
Byrne, D.J. ; Board, K.
Author_Institution :
University College of Swansea, Department of Electrical & Electronic Engineering, Swansea, UK
Abstract :
The minimisation of on-resistance of power MOSFETs is a problem of considerable importance to high-voltage MOS designers. The results of a two-dimensional simulation of VDMOS structures are presented, with linear and hexagonal surface geometries, which takes account of the finite sheet resistance of the accumulation layer under the extended gate region. A simple distributed analytic model is also introduced which gives reasonable agreement with the numerical model and which may be used to give the functional relation ship of the on-resistance with device parameters.
Keywords :
insulated gate field effect transistors; power transistors; semiconductor device models; VDMOS; accumulation layer; distributed analytic model; finite sheet resistance; hexagonal surface geometries; linear surface geometry; on-resistance minimisation; power MOSFET; two-dimensional simulation; vertical DMOS structure;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830353
