Abstract :
A fast and high-capacity electromagnetic solution, time-domain layered finite element reduction recovery (LAFE-RR) method, is proposed for high-frequency modeling and simulation of large-scale on-chip circuits. This method rigorously reduces the matrix of a multilayer system to that of a single-layer system, regardless of the problem size. More importantly, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. The recovery of solutions in all other layers involves only forward and backward substitution of matrices of single-layer size. The memory cost is also modest-requiring only the memory needed for the factorization of two sparse matrices of half-layer size. The superior performance applies to any arbitrarily shaped multilayer structure. Numerical and experimental results are presented to demonstrate the accuracy, efficiency, and capacity of the proposed method.
Keywords :
VLSI; finite element analysis; integrated circuit design; system-on-chip; LAFE-RR; high-frequency VLSI design; large-scale on-chip circuits; sparse matrices; time-domain layered finite element reduction recovery method; Central Processing Unit; Circuit simulation; Costs; Electromagnetic modeling; Finite element methods; Large-scale systems; Nonhomogeneous media; Sparse matrices; Time domain analysis; Very large scale integration; Electromagnetics; finite element methods; high frequency; on-chip circuits; time domain analysis;
