Title :
Linear-kink-noise suppression in partially depleted SOI using the twin-gate MOSFET configuration
Author :
Simoen, E. ; Claeys, C. ; Lukyanchikova, N. ; Garbar, N. ; Smolanka, A.
Author_Institution :
Interuniversity MicroElectron. Center, Leuven, Belgium
fDate :
7/1/2005 12:00:00 AM
Abstract :
The impact of using a twin-gate (TG) configuration on the gate-induced excess Lorentzian noise in thin-gate partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs has been investigated and compared with the behavior in a single-gate (SG) device. A reduction by a factor 2 of the noise overshoot amplitude at a frequency of 10 Hz can be obtained in the TG case, which is related to a similar reduction of the plateau amplitude of the Lorentzian noise component. It is shown that this decrease is generated by a lowering of the body-effect factor γB due to the presence of the inner floating n+ contact. It is believed that there, recombination of the injected holes takes place, thereby pinning the channel potential.
Keywords :
MOSFET; semiconductor device noise; silicon-on-insulator; 10 Hz; body effect factor; channel potential; gate-induced excess Lorentzian noise; injected holes; linear-kink-noise suppression; noise overshoot amplitude; partially depleted SOI; silicon-on-insulator; single-gate device; twin-gate MOSFET configuration; CMOS technology; Frequency; Low-frequency noise; MOSFET circuits; Master-slave; Noise level; Noise reduction; Semiconductor device noise; Silicon on insulator technology; Tunneling; Lorentzian noise; low-frequency noise; partially depleted (PD) silicon-on-insulator (SOI); twin-gate (TG) configuration;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2005.851178