Strongly fault-secure designs for arithmetic arrays

We make a comparative study of two techniques to design error-detectable array architectures. These techniques are the redundant binary representation (RBR) where the data is encoded in the 1-out-of-3 code; and the two-rail logic where the data is encoded in the 1-out-of-2 code. In recent work, the RBR has been used to achieve online error detection and localisation by checking the data on the array borders. Here we show that another approach is also possible, with less hardware cost, where the checking takes place at the local (processor) level. This provides immediate error detection without delay. The performance of the RBR approaches has been compared with the two-rail approach. The results show that the RBR approaches require more hardware overheads, for small word lengths (n). However, the hardware cost of the two techniques are approximately the same for large n, while the RBR approaches offer much faster arithmetics for all n.