Title :
Multilevel logic synthesis for PAL devices
Author_Institution :
Dept. of Electr. & Electron. Eng., Bristol Univ., UK
fDate :
11/1/1993 12:00:00 AM
Abstract :
A system has been developed to perform multilevel logic synthesis onto PALs for designs that will not fit in two-level sum of products form. The procedure is based upon the application of technology dependent selective collapse algorithms on a multilevel circuit. The multilevel circuit may be obtained using a number of different synthesis strategies. The packages have been implemented in C and added to SIS, the sequential synthesis system developed at Berkeley. Results compare favourably with the best previous system known.
Keywords :
logic CAD; logic arrays; many-valued logics; C; PAL devices; SIS; multilevel logic synthesis; programmable array logic devices; sequential synthesis system; technology dependent selective collapse algorithms;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
