An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator

Author

Pun, Kong-Pang ; Choy, Chiu-Sing ; Chan, Cheong-Fat ; Da Franca, José Epifânio

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, China

Volume

51

Issue

5

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

254

Lastpage

256

Abstract

This paper presents a technique to suppress the mismatch between the in-phase (I) and quadrature-phase (Q) channels of a switched-capacitor complex sigma-delta modulator that is used for the analog-to-digital conversion of a real intermediate-frequency radio signal. The mismatch is suppressed through time sharing of the critical capacitors, i.e., the input sampling capacitor and the capacitor of the feedback digital-to-analog converter, between the I and Q channels. Circuit simulations verifying the proposed technique are presented.

Keywords

analogue-digital conversion; circuit simulation; modulators; sigma-delta modulation; switched capacitor networks; I-Q mismatch; analog-to-digital conversion; circuit simulations; complex sigma-delta modulator; feedback digital-to-analog converter; in-phase channel; input sampling capacitor; intermediate-frequency; quadrature-phase channels; radio signal; switched-capacitor modulator; time sharing; Analog-digital conversion; Capacitors; Dynamic range; Energy consumption; Feedback; Filtering theory; Frequency; Mixers; Sampling methods; Time sharing computer systems; $Sigma Delta $ ; Complex sigma–delta; I/Q mismatch; IF; intermediate frequencies; modulator; sampling;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2004.827552

Filename

1299040