Title :
A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM: 1T-QW DRAM
Author :
Ertosun, M. Günhan ; Kapur, Pawan ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA
Abstract :
We propose a new kind of capacitorless DRAM: 1Transistor Quantum Well structure, which has a ldquostorage pocketrdquo for holes within the body. This memory gives the opportunity to engineer spatial hole distribution within the body of the device, which is not possible with the conventional 1T-DRAMs. Using this novel device, we demonstrate approximately two order-of-magnitude increase in the drain-current (Id) difference between the reads of two states of the memory.
Keywords :
DRAM chips; MOSFET; quantum well devices; 1T-QW DRAM; capacitorless DRAM; drain-current difference; highly scalable capacitorless double gate quantum well single transistor; storage pocket; FinFETs; Impact ionization; Impurities; Leakage current; Logic; MOSFETs; Nonvolatile memory; Random access memory; Silicon; Voltage control; DRAM; Double-gate (DG) MOSFETs; floating-body DRAM; fully depleted; scaled CMOS;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2008.2007508
