Implementations of smart pixels for optoelectronic processors and interconnection systems. I. Optoelectronic gate technology

For part II see ibid., vol. 11, no. 10, pp. 1670-1680 (Oct. 1993). Several of the common approaches to smart pixel technology, including smart pixels based on optoelectronic integrated circuits and self-electrooptic effect devices (SEEDs), are studied. An optoelectronic NOR gate pixel consisting of an output laser diode, two input photodetectors, and a transistor circuit is analyzed for the purpose of investigating overall two-dimensional (2-D) interconnection and processing system performance. The major pixel performance issues are examined. The results show that the optoelectronic logic gate has the advantages of low noise (typically ~-35 dBm), high bandwidth (>1 GHz), and low temperature sensitivity, while its power dissipation is about 5 mW, resulting in a moderate pixel packing density of 200/cm² for a total chip power dissipation of 1 W/cm²