DocumentCode :
9875
Title :
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing
Author :
Sterpone, L. ; Porrmann, Mario ; Hagemeyer, Jens
Author_Institution :
Dipt. di Autom. e Inf., Politec. di Torino, Turin, Italy
Volume :
62
Issue :
8
fYear :
2013
fDate :
Aug. 2013
Firstpage :
1508
Lastpage :
1525
Abstract :
Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today´s FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory.
Keywords :
artificial satellites; computer interfaces; fault tolerant computing; field programmable gate arrays; performance evaluation; program diagnostics; reconfigurable architectures; space vehicle electronics; FPGA configuration memory; MCU; MEU; MIL-STD-1553B; SEU; SpaceFibre; SpaceWire; blind scrubbing; component mapping; critical radiation effects; critical reconfigurable components; data processing; dynamic reconfiguration scenario; dynamically reconfigurable FPGA architecture; energy efficiency; fault injection campaigns; fault tolerance capability; information processing infrastructure; multiple event upsets; partial dynamic reconfiguration; performance optimization; radiation impact estimation; readback scrubbing; reconfigurable placed modules; routing interaction reduction; satellite payload processing; scalable prototyping environment; single event upsets; space applications; Satellite communication; Self-organizing networks; FPGA; fault injection; fault tolerance; multiple event upsets; partial reconfiguration; single event upsets; static analysis;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2013.80
Filename :
6494562
Link To Document :
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