Design and optimization of a hot-carrier resistant high-voltage nMOS transistor

Author

Annese, Marco ; Carniello, Sara ; Manzini, Stefano

Author_Institution

TPA Groups, STMicroelectronics, Milano, Italy

Volume

52

Issue

7

fYear

2005

fDate

7/1/2005 12:00:00 AM

Firstpage

1634

Lastpage

1639

Abstract

The hot-carrier degradation behavior of a class of high-voltage n-channel drift MOS transistors is experimentally investigated as a function of the geometrical (layout) parameters of the devices. The design restrictions, imposed by reliability requirements, are described as a subset of the space of the geometrical parameters (safe volume) which guarantees a safe hot-carrier operation. The optimization of the specific drain/source on-state resistance of the devices within the safe volume is discussed.

Keywords

circuit optimisation; field effect transistors; hot carriers; integrated circuit layout; power MOSFET; power integrated circuits; FET; design restrictions; device geometrical parameters; drain/source on-state resistance optimization; high-voltage field-effect transistor; hot carrier injection; hot-carrier degradation behavior; hot-carrier resistant high-voltage nMOS transistor; n-channel drift MOS transistors; reliability requirements; safe hot-carrier operation; Automotive engineering; CMOS process; Costs; Degradation; Design optimization; FETs; Hot carriers; MOSFETs; Transistors; Voltage; Hot carrier injection; high-voltage field-effect transistor (FET);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.850625

Filename

1459130