VLSI architectures for polygon recognition

Author

Sastry, Raghu ; Ranganathan, N. ; Bunke, Horst

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA

Volume

1

Issue

4

fYear

1993

Firstpage

398

Lastpage

407

Abstract

A class of VLSI architectures is proposed for the computationally intensive task of polygon recognition in 3-D space. They make use of a set of local shape descriptors for polygons that are invariant under affine transformations. The recognition procedure is based on the matching of edge length ratios using a simplified version of the dynamic programming procedure commonly used for string matching. The matching procedure also copes with partial occlusion of polygons. The architectures are systolic and fully utilize the principles of pipelining and parallelism in order to obtain high speed and throughput. A prototype VLSI chip implementing one of the proposed architectures is currently being built.<>

Keywords

VLSI; computer vision; digital signal processing chips; dynamic programming; edge detection; parallel algorithms; pattern recognition equipment; pipeline processing; systolic arrays; 3D space; VLSI architectures; affine transformations; dynamic programming procedure; edge length ratios; high speed; high throughput; local shape descriptors; matching procedure; parallelism; partial occlusion; pipelining; polygon recognition; prototype VLSI chip; systolic architecture; Computer architecture; Dynamic programming; Orbital robotics; Pipeline processing; Prototypes; Robot vision systems; Robustness; Shape; Space technology; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.250186

Filename

250186