Title :
General gate array routing using a k-terminal net routing algorithm with failure prediction
Author :
Huijbregts, Ed P. ; Jess, Jochen A G
Author_Institution :
Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
Abstract :
A general approach to gate array routing based on an abstract routing space model is presented. An efficient k-terminal net maze runner is described. It does not partition nets into two-terminal net routing problems, but solves the problem by simultaneously growing k search waves. It is shown that the explored routing space diminishes when compared to bidirectional routing schemes. Experimental data show a reduction of CPU time up to 55% and a decrease of total net length up to 6% compared to a bidirectional maze router. For k-terminal nets it is shown that net length decreases with increasing k. Additional routing space restriction is attained by use of variable search space restriction and by the introduction of a dynamic routing space partitioning method based on the concept of regions. This concept allows for determination of nonroutable nets or parts of nets in an efficient way. The new partitioning method may be implemented in any maze runner without increasing the complexity of the maze runner algorithm. Results show an additional decrease of CPU time up to 35%.<>
Keywords :
application specific integrated circuits; cellular arrays; circuit layout CAD; logic CAD; logic arrays; multiterminal networks; network routing; search problems; CPU time reduction; abstract routing space model; dynamic routing space partitioning; failure prediction; gate array routing; k-terminal net routing algorithm; maze router; net maze runner; variable search space restriction; Bidirectional control; Databases; Libraries; Partitioning algorithms; Prediction algorithms; Predictive models; Routing; Space exploration; Space technology; Wiring;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on