Integrated-circuit test structure which uses a vernier to electrically measure mask misalignment

A test structure consisting of a vernier implemented in MOS technology which may be used to electrically measure the amount of misalignment between two mask levels is described. It is ideally suited to characterise and monitor the performance of high resolution aligners such as 10:1 wafer steppers. The resolution of the vernier is limited only by the minimum grid unit permitted by the CAD system or mask resolution. The vernier is also designed to automatically compensate for any over etching which may occur during processing.