Title :
Systolic convolution array
Author_Institution :
Private Address, Cheltenham, UK
Abstract :
A systolic convolution array is presented, which has the minimum possible number of register stages, fixed fan-out, fan-in and response time, and which accepts a single input stream at the clock rate.
Keywords :
cellular arrays; integrated logic circuits; large scale integration; clock rate; fixed fan-in; fixed fan-out; register stages; response time; single input stream; systolic convolution array;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830595
