DocumentCode
989634
Title
CMOS logic circuit optimum design for radiation tolerance
Author
Hatano, Hiroshi ; Shibuya, Megumi
Author_Institution
Toshiba Corporation, Semiconductor Device Engineering Laboratory, Kawasaki, Japan
Volume
19
Issue
23
fYear
1983
Firstpage
977
Lastpage
979
Abstract
CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR.
Keywords
field effect integrated circuits; integrated logic circuits; logic design; radiation hardening (electronics); CMOS logic circuit; DC noise immunity; gate area; optimum design; radiation effects; radiation tolerance; three-input NAND; three-input NOR; transistor parameter shift data;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19830664
Filename
4248207
Link To Document