Title :
CMOS logic circuit optimum design for radiation tolerance
Author :
Hatano, Hiroshi ; Shibuya, Megumi
Author_Institution :
Toshiba Corporation, Semiconductor Device Engineering Laboratory, Kawasaki, Japan
Abstract :
CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR.
Keywords :
field effect integrated circuits; integrated logic circuits; logic design; radiation hardening (electronics); CMOS logic circuit; DC noise immunity; gate area; optimum design; radiation effects; radiation tolerance; three-input NAND; three-input NOR; transistor parameter shift data;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830664
