DocumentCode :
989667
Title :
Application of a multivariable optimiser to the design of CMOS buffers
Author :
Routley, P. ; Brunnschweiler, A. ; Ashburn, Peter
Author_Institution :
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Volume :
29
Issue :
25
fYear :
1993
Firstpage :
2187
Lastpage :
2188
Abstract :
A multivariable optimiser is used to individually optimise the size of each stage in a CMOS buffer. Then the optimiser is used to minimise the silicon area for a given buffer delay. An area saving of up to 50% is obtained, compared to other types of buffer.
Keywords :
CMOS integrated circuits; buffer circuits; circuit layout CAD; logic CAD; logic gates; CMOS buffers; area saving; buffer delay; circuit layout; logic gates; multivariable optimiser; silicon area;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19931469
Filename :
250344
Link To Document :
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