Title :
Settling time reduction technique for high speed DACs
Author :
Kim, Oleksiy ; Kim, Gracia ; Kim, Wonhee
Author_Institution :
Dept. of Electron. Eng., Seoul Nat. Univ., South Korea
Abstract :
The ringing mechanism of the high impedance output node was analysed. To reduce this ringing, a new compensation circuit was developed and implemented in a standard CMOS process. This circuit can be programmed to cover a range of parameters. It is effective in minimising the settling time of a DAC.
Keywords :
CMOS integrated circuits; compensation; digital-analogue conversion; electric impedance; CMOS process; bonding wire; compensation circuit; high impedance output node; high speed DACs; lead frame; parasitic inductance; ringing mechanism; settling time reduction technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19931472
