DocumentCode
989787
Title
Single error correcting and double error detecting coding scheme
Author
Lala, P.K. ; Thenappan, P. ; Anwar, M.T.
Author_Institution
Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA
Volume
41
Issue
13
fYear
2005
fDate
6/23/2005 12:00:00 AM
Firstpage
758
Lastpage
760
Abstract
A new coding technique for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose, except in two cases when they are almost equal to that obtained by Hsiao code. This results in simplified encoding and decoding circuitry for error detection and correction.
Keywords
error correction codes; error detection codes; parity check codes; Hsiao code; computer memory systems; decoding circuitry; double error detection; encoding circuitry; parity check matrix; single error correction;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20050614
Filename
1459887
Link To Document