DocumentCode :
990786
Title :
Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance
Author :
Sakian, P. ; Saffari, M. ; Atarodi, M. ; Tajalli, Armin
Author_Institution :
Electr. Eng. Dept., Sharif Univ. of Technol., Tehran
Volume :
2
Issue :
5
fYear :
2008
fDate :
10/1/2008 12:00:00 AM
Firstpage :
409
Lastpage :
421
Abstract :
A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 m CMOS technology and operating in 10 Gbps data rate, the entire circuit consumes 52 mW.
Keywords :
CMOS analogue integrated circuits; analogue integrated circuits; delay lock loops; frequency control; integrated circuit design; jitter; low-power electronics; synchronisation; CDR circuit; CDR system; CMOS technology; DLL clock generator; bit rate 10 Gbit/s; charge-pump-based PI; clock-and-data recovery circuit; frequency control loop; frequency-tracking ability; high-frequency tolerance; jitter; low-power analogue phase interpolator; power 52 mW; size 0.18 mum;
fLanguage :
English
Journal_Title :
Circuits, Devices & Systems, IET
Publisher :
iet
ISSN :
1751-858X
Type :
jour
DOI :
10.1049/iet-cds:20080111
Filename :
4675295
Link To Document :
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