Performance Investigation of 50-nm Insulated-Shallow-Extension Gate-Stack (ISEGaS) MOSFET for Mixed Mode Applications

Author

Kaur, Ravneet ; Chaujar, Rishu ; Saxena, Manoj ; Gupta, R.S.

Author_Institution

Semicond. Devices Res. Lab., Univ. of Delhi, New Delhi

Volume

54

Issue

2

fYear

2007

Firstpage

365

Lastpage

368

Abstract

An extended study of electrical characteristics of 50-nm single-material-gate insulated-shallow-extension-gate-stack (ISEGaS) MOSFET is performed using ATLAS-2D. Incorporation of dual-material-gate architecture leads to the suppression of short channel effects along with the improvement in device intrinsic gain (g_mtimesR_out), voltage gain (g_m/I_DS), and I_on/I_off ratio, thereby opening a new era of ISEGaS MOSFETs for mixed mode applications

Keywords

MOSFET; semiconductor device models; 50 nm; ATLAS-2D; ISEGaS; MOSFET; dual-material-gate architecture; energy-balance-transport; insulated-shallow-extension gate-stack transistor; mixed mode applications; short channel effects suppression; single-material-gate transistor; Acceleration; Avalanche breakdown; Dielectric materials; Dielectrics and electrical insulation; Doping; Electric variables; Electrons; MOSFET circuits; Semiconductor materials; Voltage; ATLAS-2D; dual material gate (DMG); energy-balance-transport (EBT); gate stack;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.888722

Filename

4067190