Title :
Use of fault dropping for multiple fault analysis
Author :
Karkouri, Younès ; Aboulhamid, El Mostapha ; Cerny, Eduard ; Verreault, Alain
Author_Institution :
Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada
fDate :
1/1/1994 12:00:00 AM
Abstract :
A new approach to fault analysis is presented. The authors consider multiple stuck-at-0/1 faults at the gate level. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis the authors consider frontier faults where there is at least a normal path from each faulty line to a primary output. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the authors evaluate the fault-free circuit and then propagate fault effects. Assuming that fault-free response is observed, a fault-dropping procedure is then applied to eliminate faulty conditions on lines, that are either absent or may be hidden by other faulty conditions. This method is applied to some benchmark circuits and achieves a high degree of efficiency
Keywords :
combinatorial circuits; logic circuits; logic testing; benchmark circuits; fault collapsing; fault dropping; fault-free circuit; frontier faults; gate level; logic circuits; multiple fault analysis; multiple stuck at faults; stuck at faults; Automatic test pattern generation; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic circuits;
Journal_Title :
Computers, IEEE Transactions on