Title :
An optimization technique for the design of multiple valued PLA´s
Author :
Asari, K. Vijayan ; Eswaran, C.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
fDate :
1/1/1994 12:00:00 AM
Abstract :
An optimization technique for the design of two types of multiple-valued PLAs is described. In a type-I PLA, the multiple-valued function is realized directly, whereas in a type-II PLA, output encoding is used to encode the binary output of the PLA. In both types, multiple function literal circuits are used for the purpose of minimization. It is shown that the proposed technique leads to a considerably reduced size of PLA when compared to the earlier techniques
Keywords :
adders; encoding; logic arrays; many-valued logics; minimisation; network synthesis; PLA size; adder; binary output; minimization; multiple function literal circuits; multiple valued PLA design; multiple valued logic; optimization technique; output encoding; programmable logic arrays; Data processing; Design optimization; Encoding; Integrated circuit interconnections; Large scale integration; Logic devices; Minimization; Multivalued logic; Programmable logic arrays; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
