• DocumentCode
    992016
  • Title

    Techniques for reducing the reverse short channel effect in sub-0.5 μm CMOS

  • Author

    Lutze, Jeffrey ; Venkatesan, Suresh

  • Author_Institution
    Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
  • Volume
    16
  • Issue
    9
  • fYear
    1995
  • Firstpage
    373
  • Lastpage
    375
  • Abstract
    Experimental evidence is presented demonstrating that the reverse short channel effect (RSCE) is initiated by damage from the source-drain implants which, in turn, causes defect-enhanced diffusion of the channel dopants toward the gate oxide interface. Several process options that attempt to modify the diffusion of the channel implants, such as channel doping profile engineering, vacancy injection into the silicon substrate through sputter-etch damage, and TEOS depositions on silicon followed by rapid thermal annealing, are described which reduce the magnitude of the reverse short channel effect. This often results in an increase in device short channel margin of as much as 50 nm and a concomitant increase in the n-channel drive current of as much as 10%.<>
  • Keywords
    CMOS integrated circuits; doping profiles; integrated circuit technology; ion implantation; rapid thermal annealing; self-diffusion; sputter etching; 0.5 micron; RTA; Si; Si substrate; TEOS depositions; channel dopants; channel doping profile engineering; defect-enhanced diffusion; gate oxide interface; n-channel drive current; rapid thermal annealing; reverse short channel effect; source-drain implants; sputter-etch damage; submicron CMOS; vacancy injection; Boron; CMOS process; Doping profiles; Implants; Joining processes; Rapid thermal annealing; Rapid thermal processing; Silicon; Thermal engineering; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.406792
  • Filename
    406792