Title :
Arithmetic unit design for neural accelerators: cost performance issues
Author :
Sammut, K.M. ; Jones, S.R.
Author_Institution :
Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
fDate :
10/1/1995 12:00:00 AM
Abstract :
Arithmetic unit design is a key issue when supporting the computational requirements of neural networks. However, there is little quantitative evidence from the study of existing neural accelerators to help choose between arithmetic constructs. This paper presents an assessment of the cost-performance trade-offs between arithmetic constructs for linear neural accelerators
Keywords :
digital arithmetic; neural nets; arithmetic unit design; cost performance issues; cost-performance trade-offs; neural accelerators; Arithmetic; Circuits and systems; Clocks; Computer architecture; Computer networks; Costs; Linear accelerators; Logic testing; Neural networks; System testing;
Journal_Title :
Computers, IEEE Transactions on
