Title :
On Cosimulating Multiple Abstraction-Level System-Level Models
Author :
Patel, Hiren D. ; Shukla, Sandeep K.
Author_Institution :
Dept. of Electr. & Comput. Engineeing, Virginia Polytech. & State Univ., Blacksburg, VA
Abstract :
SystemC´s growing community for system-level design exploration is a result of SystemC´s capability of modeling at register transfer level (RTL) and above RTL abstraction levels. However, a synthesis path from SystemC at abstraction layers above RTL is still in its infancy. A recent extension of SystemC, which is called Bluespec-SystemC electronic system level (BS-ESL), counters this difficulty with its model of computation employing atomic rule-based specifications and synthesis to Verilog. In order to simulate a model consisting of one part designed in SystemC and another using BS-ESL, we require an interoperability semantics and implementation of such a semantics. To illustrate the problem, we formalize the simulation semantics of BS-ESL and discrete-event simulation of RTL SystemC, and provide a solution based on this formalization.
Keywords :
C++ language; circuit CAD; circuit simulation; hardware description languages; Verilog; abstraction layers; atomic rule-based specifications; bluespec-SystemC electronic system level; cosimulating multiple abstraction-level; discrete-event simulation; interoperability semantics; model of computation; register transfer level; system-level models; Circuit simulation; Computational modeling; Counting circuits; Discrete event simulation; Hardware design languages; Job shop scheduling; Libraries; Processor scheduling; Registers; System-level design; Bluespec; Interoperability; Modeling and simulation; Models of Computation, , , , , ,; Simulation semantics; System Level Designs; SystemC; interoperability; modeling and simulation; models of computation; simulation semantics; system-level designs;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2007.913392