Analysis and optimization of coplanar RLC lines for GSI global interconnection

Author

Naeemi, Azad ; Davis, Jeffrey Alan ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

Volume

51

Issue

6

fYear

2004

fDate

6/1/2004 12:00:00 AM

Firstpage

985

Lastpage

994

Abstract

Compact physical models are derived for the delay and crosstalk of on-chip coplanar transmission lines, which are used in state-of-the-art high-speed microprocessors. These lines are mainly used for long global interconnects that are relatively thick and wide and have prominent inductive effects. The models are then used to optimize the design of coplanar global interconnects.

Keywords

RLC circuits; crosstalk; delays; high-speed integrated circuits; integrated circuit interconnections; integrated circuit modelling; microprocessor chips; GSI global interconnection; coplanar RLC lines; crosstalk; delay; global interconnects; high-speed microprocessors; inductance; on-chip coplanar transmission lines; physical models; repeaters; system analysis; system optimization; systems design; transmission line theory; Coplanar transmission lines; Crosstalk; Delay; Design optimization; Inductance; Integrated circuit interconnections; Microprocessors; Power system interconnection; Transistors; Wire; Crosstalk; inductance; interconnects; repeaters; system analysis and design; system optimization; transmission line theory;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2004.829517

Filename

1300835