Title :
Fault signature effectiveness of microcomputer address bus
Author_Institution :
Instytut Elektroniki, Gliwice, Poland
Abstract :
The letter presents the analysis of the effectiveness of compact testing of a microcomputer address bus with the assumed fault model SA1 and SA0, assuming that the testing schemes use a linear feedback shift register LFSR with a prime characteristic polynomial p(x) of degree n¿2.
Keywords :
computer interfaces; computer testing; fault location; logic testing; fault model; fault signature effectiveness; linear feedback shift register; microcomputer address bus; prime characteristic polynomial;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19840441
