DocumentCode :
993517
Title :
N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide
Author :
Lee, Rinus T P ; Lim, Andy Eu-Jin ; Tan, Kian-Ming ; Liow, Tsung-Yang ; Lo, Guo-Qiang ; Samudra, Ganesh S. ; Dong Zhi Chi ; Yeo, Yee-Chia
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore
Volume :
28
Issue :
2
fYear :
2007
Firstpage :
164
Lastpage :
167
Abstract :
We have fabricated n-channel 25-nm gate length FinFETs with Schottky-barrier source and drain featuring a self-aligned ytterbium silicide (YbSi1.8). A low-temperature silicidation process was developed for the formation of the low electron barrier height YbSi 1.8 phase, without reaction with SiO2 isolation or SiN spacer materials, enabling integration in a CMOS fabrication process flow. The fabricated device exhibits good device characteristics with a drive current of 241 muA/mum at VDS=VGS-Vt=1 V, Ion/Ioff=104 at VDS=1.1 V, subthreshold swing of 125 mV/decade, and drain-induced barrier lowering of 0.26 V/V
Keywords :
MOSFET; Schottky barriers; nanoelectronics; silicon compounds; ytterbium compounds; 25 nm; CMOS fabrication process flow; Schottky barrier drain; Schottky barrier source; SiN; SiO2; YbSi1.8; electron barrier height; low-temperature silicidation process; n-channel FinFET; spacer materials; ytterbium silicide; Dielectrics; Electrons; Etching; Fabrication; FinFETs; MOSFETs; Silicidation; Silicides; Silicon compounds; Ytterbium; FinFET; Schottky; YbSi; multiple-gate transistor; rare earth metal; silicide;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2006.889233
Filename :
4068952
Link To Document :
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