DocumentCode :
993555
Title :
Josephson two-bit full adder utilizing wide margin functional gates
Author :
Ichimiya, Y. ; Yamada, H. ; Ishida, A.
Author_Institution :
NTT, Tokyo, Japan
Volume :
19
Issue :
3
fYear :
1983
fDate :
5/1/1983 12:00:00 AM
Firstpage :
1178
Lastpage :
1181
Abstract :
A Josephson two-bit full adder circuit with wide margin functional gates has been studied. The adder circuit is comprised of functional exclusive-OR (EXOR) gates for sum operation and majority gates for ripple carry operation. A wide margin EXOR gate was constructed with serial connection of two double-input asymmetrical interferometers (AILs), in which two input lines were coupled to the interferometers with such an arrangement that the input-induced magnetic fluxes electromagnetically cancel each other. For majority gates, gate-to-input coupling should be made uniform for all three inputs. For this purpose, three input lines were laid in parallel on the loop of triple-input planar interferometer, so that one of two outer lines ran along the loop outside the edge but returned along the inside and the other vice versa. By using these functional gates a full adder circuit can be constructed with only three gates/bits. Experimentally, the two-bit parallel adder circuit was fabricated by standard Pb-alloy technology with 5μm line width. Two-bit parallel full adder operation was successfully performed. Additionally, operating margin over ±10% for the bias was obtained for each gate.
Keywords :
Addition; Josephson device logic gates; Adders; Coupling circuits; Electrodes; Electromagnetic coupling; Equations; Interferometers; Josephson junctions; Laboratories; Logic gates; Voltage;
fLanguage :
English
Journal_Title :
Magnetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9464
Type :
jour
DOI :
10.1109/TMAG.1983.1062329
Filename :
1062329
Link To Document :
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