Title :
A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance
Author :
Lin, Chien-Ting ; Fang, Yean-Kuen ; Yeh, Wen-Kuan ; Lee, Tung-Hsing ; Chen, Ming-Shing ; Lai, Chieh-Ming ; Hsu, Che-Hua ; Chen, Liang-Wei ; Cheng, Li-Wei ; Ma, Mike
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
Abstract :
A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the NixSi FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance ION. For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the ION of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data
Keywords :
CMOS integrated circuits; X-ray diffraction; nickel compounds; phase transformations; rapid thermal processing; silicon compounds; tensile strength; transmission electron microscopy; 90 nm; CESL; FUSI gated CMOS performance; NixSi; X-ray diffraction spectrum; contact etch stop layer; fully silicided metal gate; phase transfer; rapid thermal process; strain engineering; tensile stress; transmission electron microscope cross section analysis; CMOS process; Capacitive sensors; Electrodes; Etching; Rapid thermal processing; Silicides; Silicon compounds; Tensile strain; Tensile stress; Thermal stresses; Contact etch stop layer (CESL); fully silicided (FUSI); phase transfer; strain engineering; tensile stress;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.889633
