Title :
Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors
Author :
Park, Ki-Heung ; Lee, Jong-Ho
Author_Institution :
Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Daegu
Abstract :
We proposed a new bulk FinFET that has a p+/n+ poly-Si gate consists of p+ region near the source and n+ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n+ poly-Si gate length (Ls). For given gate length (Lgles50 nm) and fin body width (Wfinles30 nm), Ls was designed to satisfy the I off requirement (i.e., 1 fA) of DRAM cell. Optimum Ls /Lg of 30-nm device was ~0.4 at a Wfin of 10 nm and ~0.2 at a Wfin of 15 nm
Keywords :
DRAM chips; MOSFET; silicon; work function; 10 nm; 15 nm; 30 nm; 50 nm; DRAM cell transistors; FinFET; Si; gate-induced drain leakage; work function; Business; Doping; Electronic mail; FinFETs; Nonvolatile memory; Performance evaluation; Plasma immersion ion implantation; Random access memory; Threshold voltage; Transistors; DRAM; FinFET; dual poly-gate; gate-induced drain leakage (GIDL); workfunction;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.889235
