• DocumentCode
    993684
  • Title

    2 Gbit/s regenerator using commercial silicon bipolar circuits

  • Author

    White, B.R.

  • Author_Institution
    British Telecom Research Laboratories, Ipswich, UK
  • Volume
    20
  • Issue
    16
  • fYear
    1984
  • Firstpage
    669
  • Lastpage
    670
  • Abstract
    A regenerator for fibre optic systems which operates at 2 Gbit/s has been demonstrated using commercially available silicon bipolar integrated circuits. A parallel processing technique with following interleaver is used to achieve the required decision gate function. The regenerator has an ¿2 mV front end sensitivity for a<1 in 109 BER with a 215¿1 PRBS.
  • Keywords
    digital circuits; optical communication equipment; optical fibres; parallel processing; decision gate function; fibre optic systems; front end sensitivity; parallel processing technique; regenerator;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19840458
  • Filename
    4248948
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=993684