Logic simulation with current-limited switches

Author

Ruan, Genhong ; Vlach, Jiri ; Barby, James A.

Author_Institution

Analogy Inc., Beaverton, OR, USA

Volume

9

Issue

2

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

133

Lastpage

141

Abstract

A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff´s laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulation

Keywords

MOS integrated circuits; circuit analysis computing; fault location; integrated logic circuits; logic CAD; Kirchoff´s laws; MOS networks; current-limited switches; fault simulation; line-open fault; node-short fault; open circuit; short circuit; switch-level logic simulator; switch-level timing simulator; CMOS logic circuits; Circuit faults; Circuit simulation; Computational modeling; Discrete event simulation; Equations; Switches; Timing; Variable structure systems; Voltage;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.46779

Filename

46779