Abstract :
Over the past few years, the ARM reduced-instruction-set computing (RISC) processor has evolved to offer a family of chips that range up to a full-blown multiprocessor. Embedded applications´ demand for increasing levels of performance and the added efficiency of key new technologies has driven the ARM architecture´s evolution. Throughout this evolutionary path, the ARM team has used a full range of techniques known to computer architecture for exploiting parallelism. The performance and efficiency methods that ARM uses include variable execution time, subword parallelism, digital signal processor-like operations, thread-level parallelism and exception handling, and multiprocessing. Leveraging parallelism on several levels, ARM´s new chip designs could change how people access technology. With sales growing rapidly and more than 1.5 billion ARM processors already sold each year, software writers now have a huge range of markets in which their ARM code can be used.
Keywords :
instruction sets; microprocessor chips; parallel architectures; parallel programming; reduced instruction set computing; ARM RISC processor; ARM chip design; ARM instruction set architecture; digital signal processor-like operations; exception handling; multiprocessing; reduced-instruction-set computing; subword parallelism; thread-level parallelism; variable execution time; Computer aided instruction; Computer architecture; Data processing; Digital signal processing; Instruction sets; Parallel processing; Process design; Reduced instruction set computing; Registers; Thumb; MPSoCs; RISC processors; computer architectures; multiprocessor systems;
