DocumentCode
994283
Title
CMOS design technique to eliminate the stuck-open fault problem of testability
Author
Murray, A.F.
Author_Institution
University of Edinburgh, Wolfson Microelectronics Institute, Edinburgh, UK
Volume
20
Issue
19
fYear
1984
Firstpage
758
Lastpage
760
Abstract
A dynamic CMOS design style is described, which utilises both N-type and P-type logic blocks and avoids the problems in generating tests for stuck-open faults. The testability of the resultant logic is examined analytically and fault simulation results are presented.
Keywords
field effect integrated circuits; integrated circuit testing; integrated logic circuits; logic design; logic testing; N-type logic blocks; NORA CMOS; P-type logic blocks; VLSI; dynamic CMOS design style; fault simulation results; generating tests for stuck-open faults; logic design; logic testing; stuck-open fault problem; test problem elimination; testability;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19840516
Filename
4249023
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