Title :
CMOS design technique to eliminate the stuck-open fault problem of testability
Author_Institution :
University of Edinburgh, Wolfson Microelectronics Institute, Edinburgh, UK
Abstract :
A dynamic CMOS design style is described, which utilises both N-type and P-type logic blocks and avoids the problems in generating tests for stuck-open faults. The testability of the resultant logic is examined analytically and fault simulation results are presented.
Keywords :
field effect integrated circuits; integrated circuit testing; integrated logic circuits; logic design; logic testing; N-type logic blocks; NORA CMOS; P-type logic blocks; VLSI; dynamic CMOS design style; fault simulation results; generating tests for stuck-open faults; logic design; logic testing; stuck-open fault problem; test problem elimination; testability;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19840516
