DocumentCode
994466
Title
An efficient algorithm for constrained encoding and its applications
Author
Shi, Chuan-Jin ; Brzozswski, J.A.
Author_Institution
Dept. of Comput. Sci., Waterloo Univ., Ont., Canada
Volume
12
Issue
12
fYear
1993
fDate
12/1/1993 12:00:00 AM
Firstpage
1813
Lastpage
1826
Abstract
An efficient algorithm and its implementation, ENCORE, are presented for finding approximate solutions to dichotomy-based constrained encoding, a problem fundamental to the synthesis of combinational logic circuits, and synchronous and asynchronous sequential circuits. ENCORE adopts a greedy strategy to find an encoding bit by bit, and then uses an iterative method to improve the solution quality. The novelty of the algorithm lies mainly in a linear-time heuristic to select each individual bit; this problem was previously solved in quadratic time. ENCORE has been applied to a variety of practical problem instances. For a number of examples found in the literature on the synthesis of asynchronous sequential machines, ENCORE consistently obtains optimal or near-optimal results. For the optimum state assignment of the MCNC FSM benchmarks, ENCORE generates the same or even shorter encoding lengths than the programs KISS, NOVA and DIET, but takes much less CPU time. It is demonstrated for the first time that PLA implementations of synchronous FSMs using dichotomy constraints compare very favorably with respect to area with those based on traditional group constraints
Keywords
combinatorial circuits; encoding; finite state machines; iterative methods; logic CAD; logic arrays; sequential circuits; ENCORE; MCNC FSM benchmarks; PLA implementations; asynchronous sequential circuits; combinational logic circuits; dichotomy-based constrained encoding; encoding lengths; iterative method; linear-time heuristic; logic design; synchronous FSMs; synchronous sequential circuits; Asynchronous circuits; Central Processing Unit; Circuit synthesis; Combinational circuits; Encoding; Iterative algorithms; Iterative methods; Logic circuits; Programmable logic arrays; Sequential circuits;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.251145
Filename
251145
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