A unified approach to floorplan sizing and enumeration

Author

Yeap, Gary Kok-Hoo ; Sarrafzadeh, Majid

Author_Institution

Semicond. Syst. Des. Technol. Group, Motorola Inc., Tempe, AZ, USA

Volume

12

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1858

Lastpage

1867

Abstract

Given a sliceable floorplan and cell sizes, Otten and Stockmeyer [1983] presented an algorithm to find an optimal implementation for each cell. The authors consider a generalized optimal sizing problem on a set of slicing trees related to an adjacency graph. For computation efficiency, they combine the tree enumeration and sizing procedures in a unified algorithm where floorplan trees and sizes are computed simultaneously. The tree enumeration is based on adjacency graph of the input cells, which ensures that the adjacency requirements of the cells are preserved. Time complexity of the algorithm is analyzed and experimental results using MCNC benchmarks are reported

Keywords

VLSI; circuit layout CAD; computational complexity; trees (mathematics); MCNC benchmarks; VLSI layout; adjacency graph; cell sizes; floorplan sizing; sliceable floorplan; slicing trees; time complexity; tree enumeration; Algorithm design and analysis; Analog circuits; Cost function; Dynamic programming; Helium; Linear programming; Partitioning algorithms; Polynomials; Terminology; Tree graphs;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.251149

Filename

251149