Analysis of hot-carrier-induced degradation mode on pMOSFET´s

Author

Matsuoka, Fumitomo ; Iwai, Hiroshi ; Hayashida, Hiroyuki ; Hama, Kaoru ; Toyoshima, Yoshiaki ; Maeguchi, Kenji

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

37

Issue

6

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

1487

Lastpage

1495

Abstract

Hot-carrier-induced degradation surface-channel (p⁺ polysilicon gate) and buried-channel (n⁺ polysilicon gate) pMOSFETs is discussed. In the shallow gate bias region, a hot-carrier degradation mode by drain avalanche hot hole injection was found for the surface-channel pMOSFETs. Trapped holes and interface state generation, which were not observed in the buried-channel pMOSFETs, were detected. In this gate bias region, the degradation for the surface-channel structure is smaller than that for the buried-channel structure. Three reasons for the smaller degradation in the surface-channel structure are discussed. The deep-gate bias region was also investigated. In this region, an interface-state generation mode without the threshold-voltage shift was found for both surface- and buried-channel pMOSFETs. This interface state generation is caused by channel hot hole injection

Keywords

hot carriers; insulated gate field effect transistors; semiconductor device models; buried-channel; channel hot hole injection; deep-gate bias region; drain avalanche hot hole injection; hot-carrier-induced degradation mode; interface state generation; pMOSFETs; polysilicon gate; scaling; surface-channel; Charge carrier processes; Degradation; Electron traps; Hot carriers; Impact ionization; Interface states; MOSFET circuits; Silicon; Subthreshold current; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.106244

Filename

106244