Abstract :
Results of Monte Carlo simulations of the tolerances of Josephson logic devices are presented. The Monte Carlo analysis was carried out for a large number of cases; for each case, the circuit parameters were randomly selected from their assumed statistical distributions. This technique facilitated the handling of complex, non-Gaussian distributions that can exist for the process parameters. These tolerance calculations included the effects of thermal noise, variations in voltage regulation, and power bus disturbs. To reduce computing time, analytical approximations to the threshold curves of the devices were used. Typically, 10,000 to 100,000 cases were analyzed for a given set of assumptions on parameter variations. This size of simulation allows one to estimate, with a high degree of confidence, the tolerance-limited yield of a chip containing 1000 devices. The Monte Carlo analysis, for 10,000 cases, used approximately three minutes of computing time on an IBM 3033.
