Title :
Logic synthesis for manufacturability
Author :
Nardi, Alessandra ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
Design optimization during synthesis is for area and/or performance while optimization for yield occurs at the layout level. To obtain abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis. Design for manufacturability denotes all techniques designers use to estimate and control yield and robustness during the design phase, prior to manufacturing.
Keywords :
design for manufacture; integrated circuit layout; integrated circuit yield; logic design; optimisation; design for manufacturability; design for yield; integrated circuit design optimization; integrated circuit layout; logic synthesis; Circuit synthesis; Cost function; Design optimization; Libraries; Logic design; Manufacturing; Process design; Redundancy; Robustness; Routing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2004.15
