Title :
Defect and error tolerance in the presence of massive numbers of defects
Author :
Breuer, Melvin A. ; Gupta, Sandeep K. ; Mak, T.M.
Author_Institution :
Univ. of Southern California, Los Angeles, CA, USA
Abstract :
As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. We introduce a new approach for error tolerance resulting in chips containing only error acceptable for such applications.
Keywords :
error statistics; fault simulation; fault tolerance; integrated circuit reliability; integrated circuit testing; integrated circuit yield; logic testing; defect tolerance; error statistics; error tolerance computing; fault simulation; fault tolerance; integrated circuit reliability; integrated circuit testing; integrated circuit yield; logic testing; Circuit faults; Costs; Fabrication; Fault tolerance; Logic design; Logic devices; Logic testing; Manufacturing; Noise level; Redundancy;
Journal_Title :
Design & Test of Computers, IEEE
