Title :
New challenges in delay testing of nanometer, multigigahertz designs
Author :
Mak, T.M. ; Krstic, Angela ; Cheng, Kwang-Ting Tim ; Wang, Li.-C.
Author_Institution :
Design Technol. Group, Intel, Santa Clara, CA, USA
Abstract :
Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. We examine the challenges in meeting the quality requirements of gigascale integration, and explore functional testing as well as statistical models and methods that could alleviate some of those problems.
Keywords :
built-in self test; delay estimation; design for testability; integrated circuit testing; statistical analysis; DFT; deep-submicron design; design for testability; functional testing; gigascale integration; integrated circuit testing; path delay; statistical method; Circuit noise; Copper; Crosstalk; Delay; Geometry; Integrated circuit interconnections; Shape; Testing; Timing; Transistors;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2004.17
