• DocumentCode
    995527
  • Title

    DFT for delay fault testing of high-performance digital circuits

  • Author

    Chatterjee, Bhaskar ; Sachdev, Manoj ; Keshavarzi, Ali

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
  • Volume
    21
  • Issue
    3
  • fYear
    2004
  • Firstpage
    248
  • Lastpage
    258
  • Abstract
    Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.
  • Keywords
    CMOS logic circuits; design for testability; fault simulation; integrated circuit reliability; integrated circuit testing; logic testing; DFT technique; design for testability; fault testing; footer transistor; high performance digital circuit; integrated circuit testing; logic gate; CMOS logic circuits; Circuit faults; Circuit testing; Clocks; Delay; Digital circuits; Logic gates; Logic testing; MOS devices; Timing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2004.10
  • Filename
    1302091
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=995527